Compilation and transpilation fundamentals
Compile a logical circuit for a target and verify its meaning after routing and layout changes.
- Explain the role of target gates and connectivity.
- Compile at several optimisation levels.
- Compare a routed circuit with layout-aware equivalence.
Begin with a clear question
Section titled “Begin with a clear question”A processor accepts particular instructions on particular qubits. Transpilation translates a logical circuit into that target’s instructions, adding routing where needed and simplifying where possible. The useful question is whether the compiled program preserves the intended behaviour within the approximation settings you allowed.
Build the reasoning
Section titled “Build the reasoning”A CX between distant logical wires may require movement through intermediate physical qubits. The final wire labels can therefore differ from the original logical layout. Comparing raw matrices without accounting for that permutation can report a false failure. Conversely, ignoring layout when processing counts can turn a correct physical run into an incorrect classical answer.
Worked example
Section titled “Worked example”Create a three-qubit line target, then request an interaction between the ends. Compile at four optimisation levels with a fixed transpiler seed. Operator.from_circuit uses the compiled circuit layout for this comparison. The depth and operation counts measure the compiled small example; they are not a hardware timing benchmark.
from qiskit import QuantumCircuitfrom qiskit.quantum_info import Operatorfrom qiskit.providers.fake_provider import GenericBackendV2from qiskit.transpiler.preset_passmanagers import generate_preset_pass_manager
backend = GenericBackendV2(3, coupling_map=[[0,1],[1,0],[1,2],[2,1]], seed=42)logical = QuantumCircuit(3)logical.h(0); logical.cx(0, 2)reference = Operator.from_circuit(logical)for level in range(4): pm = generate_preset_pass_manager(backend=backend, optimization_level=level, seed_transpiler=42) compiled = pm.run(logical) assert Operator.from_circuit(compiled).equiv(reference) print(level, compiled.depth(), dict(compiled.count_ops()))Practical lab
Section titled “Practical lab”Inspect native instruction support and coupling constraints as notebook 03 does. Save the target description, optimisation level, transpiler seed and final layout with your results. Dense unitary checks are small-instance tools; larger programs need appropriate equivalence methods and task-specific checks. Calibration-weighted choices may change when the target changes, so recompile against the target you actually execute.
Run the corresponding notebook from the software practice collection:
- Download Transpilation: change the circuit, preserve its meaning
- Download A tested local workflow and an explicit hardware handoff
Keep a short execution record: predicted result, observed result, environment, inputs and the check that would reject a plausible defect. Explain a failure before changing the expected value.
Chapter summary
Section titled “Chapter summary”- Compile for an explicit target.
- Include layout when verifying and decoding.
- Record resource counts and execution settings.
Exercises
Section titled “Exercises”- Two compiled circuits have equal depth but different two-qubit gate counts. Is their expected reliability necessarily equal?
- Change one part of the worked program to create a plausible fault. State which assertion should fail and why.
Worked answers
- No. Gate types, locations, calibrations, idle time, routing and correlations matter. Depth alone is an incomplete resource or noise model.
- A useful answer identifies a specific changed gate, parameter, mapping or model and links it to an independent expected behaviour. Keep the intended specification fixed while changing the implementation; save the failing case as a regression test.
Check your understanding
Section titled “Check your understanding”Why might a direct raw-matrix comparison reject a correct routed circuit?
Answer: The logical-to-physical layout permutation was omitted. Recover the intended logical ordering before comparing behaviour.
Sources
Section titled “Sources”IBM’s bit-ordering guide, Statevector API and Operator API describe the SDK conventions and equivalence tools. IBM’s pass-manager guide describes target compilation. The notebook bundle records its pinned environment and local execution evidence.
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